The present invention relates to a semiconductor integrated circuit device and a method for fabricating the same, and it relates, more particularly, to such a device that includes a resistor and a capacitor together with an insulated gate transistor on a single semiconductor substrate and to a method for fabricating the same.
A semiconductor integrated circuit device required not only insulated-gate field-effect transistors (hereinafter referred to as an IGFETs) but also one or more capacitors and one or more resistors. There are known various types of capacitors. As a typical capacitor, a metal-oxide-semiconductor (MOS) capacitor is employed. In the MOS capacitor, further, it is proposed in Japanese Patent Laid-open Publication No. SHO 63-94664 that the dielectric film is made of a stacked structure of a silicon nitride film and a silicon oxide film to reduce the leakage current and to increase the capacitance value.
There are also known various types of resistors. One of them is a polysilicon resistor formed on an insulating film covering the semiconductor substrate. This resistor is made of a polysilicon film with a certain sheet resistance and with certain width and length to present a required resistance value, as disclosed in Japanese Patent Publication No. SHO 58-26178.
Thus, the device including the IGFET, the capacitor and the resistor is constructed by such a structure as shown in FIG. 5.
Specifically, a field oxide film 2 is selectively formed on the main surface of a P-type silicon substrate 1 to define an active area for an IGFET 30. This IGFET 30 includes a gate oxide layer 34 formed on the active area of the substrate 1 and a gate electrode 35 of a polycide structure comprising a polysilicon layer 11 and a silicide film 12 formed on the gate oxide layer 34. A pair of N-type impurity regions 36 and 37 as a source and a drain are formed in a self-aligned manner with the gate electrode 35 and the field oxide layer 11.
On the other hand, a capacitor 60 and a resistor 70 are formed on the field oxide film 2. The capacitor 60 includes a lower electrode portion 64 and an electrode led-out portion 64A each made of a polysilicon layer with a low sheet resistance. Formed on the electrode portion 64 is a stacked dielectric film 65 comprising a silicon oxide film 61 and a silicon nitride film 62. An upper electrode 68 made of aluminum and the like is formed on the dielectric film 65.
The resistor 70 is formed on a polysilicon layer 74 with a sheet resistance higher than that of the polysilicon layer 64 (64A).
These FET 30, capacitor 60 and resistor 70 is covered with inter-layer insulation layer 71 such as a silicon oxide film in which contact holes 66 and 76 are selectively formed. An lower leading-out electrode 67 is connected through the contact hole 66 to the electrode led-out portion 64A, and an electrode 77 is connected through the connecting bore 76 to one end of the polysilicon layer 74 of the resistor 70.
In this semiconductor integrated circuit device, however, the higher sheet resistance polysilicon layer 74 is used as the resistor 70 and the lower sheet resistance polysilicon layer 64 (64A) is used as the lower electrode of the capacitor 60. These layers are therefore required to be deposited by the different steps. For this reason, an alignment error occurs in the relative position relationship between the resistor 70 and the capacitor 60, resulting in restriction in high densification. Moreover, the device fabrication becomes inevitably complicated to make the cost thereof high.
Furthermore, the interlayer insulating film 71 is deposited thick directly on the upper surface of the resistor layer 74. For this reason, the resistance value of the resistor 70 becomes unstable due to the stress from the insulating layer 71 and/or a movement of positive ions therethrough.